Technology
A high-power pump that de-risks your supply, not just a line on the BOM.
The first engine on the platform.
The pump is where the platform shows up first: it runs uncooled, has no facet to fail by COD, and is built on an allied Taiwan-and-US chain, so you can qualify and reproduce it on your own bench. We don't lead with $/W: a pump is 1–2% of a machine's cost. We lead with total cost of ownership and qualification. For fusion-class systems, where the pump is roughly a third of the BOM, that's where the economics actually move. The building blocks are proven; integration is the bet, and one we'd rather take on with you.
Architecture
Two ways to build a semiconductor pump.
Surface emitters fire off the 2-D wafer face: no facet, no stacking, litho-set wavelength.
They differ in one thing that cascades into everything: where the light leaves the chip. An edge-emitting bar fires from a 1-D cleaved facet, so it must be stacked; its wavelength is gain-set and drifts ~0.3 nm/K; the facet is where COD ends it. A surface emitter fires off the 2-D wafer face instead: no facet, no COD, wavelength set by lithography and steady to ~0.06 nm/K. VCSEL and PCSEL are one family on that wafer process; a photonic crystal holds each ~1 mm PCSEL aperture in a single coherent mode, so power and brightness climb the same curve, ramping ~10× over five years. PCSEL is the one we build.
| Property | Edge-emitting laser (EEL, the incumbent) | Surface-emitting laser (PCSEL, what we build) |
|---|---|---|
| Emission | 1-D cleaved facet | 2-D wafer surface |
| Divergence | wide, asymmetric (~40°×10°) | ~0.1°, single coherent mode |
| Wavelength set by | the gain peak | lithography (the photonic crystal) |
| Wavelength stability | ~0.3 nm/K | ~0.06 nm/K |
| Reliability | facet-limited (COD) | facet-free, no COD |
| Power (single emitter) | high, but must be stacked | ~1 mm aperture, ramping ~10× over five years |
| Wall-plug efficiency | mature | ramping; the open item |
| Cost trajectory | serial labor floor | wafer curve, runs under it |
Economics
$/W isn't the axis. Here's how the pump reaches your number.
Manufacturing structure first, then the three levers to whatever you're judged on.
First, why cheaper diode bars don't threaten the case: edge-emitters are built serially (cleave, mount, align, stack), so their cost floor is set by labor, not wafer area, which is why bar prices flattened. A surface emitter is monolithic 2-D, built and tested at wafer level, so cost tracks wafer area and yield and keeps falling with volume: VCSEL already rode 3-D sensing to ~$0.05–0.10/W, and the photonic-crystal source shares ~80% of that process. The edge-emitter floor is structural; our curve runs under it.
What an inertial-fusion plant can spend on diodes versus what one plant needs made every year: neither wall is physics. Figures are per peak optical watt.
- Plant CAPEX
- $4 to 6 billion
- Laser driver
- about $1.75 billion, 35% of plant CAPEX
- Diodes
- about $0.5 billion, roughly a third of the driver
- Required diode price
- about $0.01 per watt — that $0.5B has to buy the driver’s full ~50 GW of peak optical power
- One plant’s need
- ~50 GW peak optical power
- World output today
- ~18 million bars a year at 500 W to 1 kW each, i.e. 9 to 18 GW
- Time to supply one plant
- 3 to 6 years of the whole world’s output
The edge-emitting bar’s cost floor is labour, not wafer area, so bar prices sit at $0.30 to $1.30 per watt today; the surface emitter is built and tested at wafer level, so its cost tracks area and yield and runs under that floor toward what an inertial-fusion plant requires.
- Edge-emitting bar
- $0.30 to $1.30 per watt today; floor set by labour — each bar needs its own submount and lens alignment — not wafer area
- Surface emitter
- built and tested at wafer level, so cost tracks area and yield and keeps falling with volume
- Target
- what an inertial-fusion plant requires
- Axis
- $/W on a log scale ($1, $0.10, $0.01) against cumulative volume
Then, how that reaches your economics. Whatever your top-line metric (LCOE for energy and fusion, cost-per-engagement or uptime for defense, TCO for industrial), the pump moves it through three levers, and we're precise about where each stands.
Availability is inherent: no-COD reliability lifts your capacity factor, and it is structural to surface emission, not a number we have to hit.
Capex rides a proven curve: the wafer cost mechanism VCSEL already demonstrated, which PCSEL inherits through its ~80% shared process.
Opex is the ramp: wall-plug efficiency sets your power and cooling, and it is still climbing toward the target, the part we are openly still proving.
You own the top-down system model; we bring the bottom-up pump cost stack. Overlaying the two is the fastest, lowest-risk way to see whether the surface emitter moves your number, before anyone touches hardware.
Maturity
The building blocks are proven; integration is the bet.
We state the open item up front.
Device manufacturing, spectral match, brightness and reliability are demonstrated or ahead. Wall-plug efficiency is ramping, ~50–60% today. The thermal path is adjacent-proven. The one gating item is areal power density at the pulse, and we say so up front rather than bury it. The gap is power density and ramp, not fabrication: coupling, wavelength and reliability are learnable now on an available 2-D source, and high-power PCSEL is the longer bet.
| Capability | State | What stands behind it |
|---|---|---|
| Device manufacturing | validated | PCSEL and high-power VCSEL arrays already built on the line |
| Spectral match | validated | wavelength set by the lattice, native to the structure |
| Brightness | validated | ~1 GW·cm⁻²·sr⁻¹, far above a flood-pump floor |
| Reliability | partly validated | the COD failure mode is designed out; lifetime under duty not yet logged |
| Wall-plug efficiency | partly validated | climbing; no published PCSEL array figure yet |
| Thermal path | validated elsewhere | die-attach, submount and cooler stack already qualified on high-power bars |
| Areal power density | to be validated | at the pulse: the one gating item, stated up front |
Co-development
We want your problem, not just to pitch ours.
A co-development partner, not a vendor pitch.
The unknowns are real enough that we'd rather iterate together and share the IP that comes out of it. Three things to establish jointly: coupling inside a high-rep driver, wavelength and thermal stability under duty, and real lifetime versus bars. A low-risk way to start: a single-amplifier or bench test kept off your critical path, grown into a milestone program around your constraints. We're an early team, and we mean that as a strength: we'll shape the program around what's genuinely useful to you.
Common questions
Straight answers.
- What can I buy, and why is it better?
- A high-power SEL pump: uncooled, no-COD, supply-secure (Taiwan + US), reproducible.
- What are my options, and why surface-emitting?
- Two architectures; the surface emitter drops the facet and the stacking, so wavelength, reliability and cost improve at once.
- Won't cheaper bars undercut you, and how does this move MY number?
- Different cost mechanism (wafer curve under the serial floor); then capex + opex + availability map to your metric; let's model it before hardware.
- Is this real, or a lab demo, and where's the risk?
- Building blocks proven; the one open item is areal power density at the pulse; the risk is ramp, not fabrication.
- What are you actually asking for?
- A co-development partner; a low-risk bench start, grown into a milestone program.
- How do I start?
- Send your specs, or the problem you want solved.
Talk specs.
Wavelength, power, duty cycle, or bring the pain you actually have.
Tell us what you need the light to do. We'll tell you what's on the wafer.